This disclosure relates to assessing and forecasting the degradation of PMOS and NMOS circuit elements by comparing the operating characteristics of elements when stressed by voltage biasing conditions, versus operating characteristics of the same or other similar elements when not stressed.
Metal oxide semiconductor field effect transistors (MOSFET) are subject to physical effects that degrade operating characteristics, temporarily with stress or permanently due to accumulating effects of stress and/or operational conditions. In digital integrated circuits, the devices typically are provided in complementary MOS pairs with an NMOS element and a PMOS element coupled in series across a potential difference. One complementary element is conductive and the other nonconductive in any given logic state, which situation is reversed when switched to the other logic state. Although durable and long-lived as a class of devices, physical degradation of MOS devices occurs, and is a concern, particularly as the devices are scaled to very small dimensions in densely arranged integrated circuit designs.
Conditions leading to degradation can relate to gate bias voltage conditions and/or source/drain bias voltage conditions. Some physical effects that degrade MOS devices and receive attention due to design and reliability considerations are Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), which is negative (NBTI) for PMOS devices and positive (PBTI) for NMOS), and Time Dependent Dielectric Breakdown (TDDB). Signs of degradation may include an increase in the threshold voltage of a device, progressively greater conductivity through the gate dielectric, changes in on or off current levels, etc.
Hot carrier injection (HCI) concerns the tendency of charge carriers flowing from source to drain to attain energy causing ionization and release of additional charge carriers, or causing some charge carriers to be injected into the dielectric layer by which the gate is insulated from the conduction channel between the source and drain. The charge carriers produce charge traps and material changes near the interface, leading to changes in performance characteristics such as threshold voltage, transconductance and/or saturation current. The rate of degradation due to hot carrier injection is a function of channel length, dielectric thickness and operational bias voltage.
Negative bias temperature instability (NBTI) is primarily a degradation effect for P-channel MOS transistors subjected to negative gate/substrate voltages. Holes are trapped at the interface between the gate oxide layer (typically SiO2) and the substrate (Si). This type of degradation decreases absolute drain current and transconductance. The absolute “off” current level and the threshold voltage are increased. There is a tendency for devices affected by NBTI to recover after stress is relieved.
One can also identify positive bias temperature instability (PBTI) in N-channel devices. The PBTI effect for N-channel devices is less than the NBTI effect for P-channel devices, e.g., in SiO2/poly-gate technology. However in high-k metal gate technology, the PBTI effect should be taken into account. Thus, it is advantageous to consider both positive and negative bias temperature instability in assessing and forecasting device degradation.
Time dependent dielectric breakdown (TDDB), also known as oxide breakdown, occurs from localized hole and bulk electron traps in the gate oxide layer. The degradation is accelerated by applying a high amplitude electric field across the anode and cathode of the gate insulator. Damage to the oxide affects its characteristics, especially current leakage through the dielectric. As the damage accumulates, conductor traps that are located near one another form percolation conductive paths through the oxide layer. Increased current along such lower resistance conductive paths causes heating. With progressive TDDB degradation, the device continues to operate while its specifications deteriorate, unless or until a conductive path shorts through the oxide layer, making the gate inoperable.
The issue of circuit degradation is increasingly important as circuits are scaled to smaller and smaller sizes. It is appropriate when reducing the size of MOS devices also to reduce drive and bias voltages. However, in some designs, tradeoffs are made, and perhaps size is scaled down more than drive voltage, leading to added stress.
Integrated circuits employing MOS transistors are designed with the expectation of operating characteristics within specified ranges and tolerance. When the degradation of particular elements causes its operational characteristics to fall out of the range for which the circuit was designed, the integrated circuit may fail. It is advantageous to test circuit designs for MOS degradation when in the design process. It is also useful to provide an on-board technique by which the progressive degradation of MOS elements can be watched and monitored. Suitable alarms can be raised, or corrective action taken if the degradation becomes severe.
Testing products for durability often involves applying stress. In order to assess durability in a time that is shorter than a device's normal lifetime, stress is applied for testing purposes at levels that are greater than the levels of stress expected in normal use. With test MOS devices, stress tests can include applying high voltage bias, high input signal levels, elevated current density conditions and the like. The measured reliability and durability of samples tested under elevated levels of stress produce inferences about the likely reliability and durability of the production output of devices of the same or similar type, presumed to be used at nominal conditions rather than elevated stress conditions. The same sort of testing used for projecting reliability can be applied to production samples for quality assurance testing. Also, samples with different alternative materials or dimensions can be compared by comparing their operating characteristics after stress testing.
One technique for testing sample CMOS transistors, for predicting the longevity of products of similar design and/or the results of similar production steps, is to compare two test circuits embodied with similar or identical transistors in the same configuration, wherein one is particularly stressed and the other is not. An on-board device for this purpose is disclosed in Kim, T. H. et al., “Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits,” IEEE Journal of Solid State Circuits, 43:4, pp. 874-880, April 2008. This device is based on providing two ring oscillators, each oscillator comprising a plurality of cascaded inverters connected in a closed loop. Each inverters comprises a PMOS element and an NMOS element in a complementary pair. One of the ring oscillators is relatively more stressed by applying a relatively high bias voltage to the inverters of the ring oscillator. The other ring oscillator is operated as a control for purposes of comparison, relatively less-stressed at a lower or nominal bias voltage.
As stated above, one of the effects of degradation is an increase in the threshold voltage of the degraded MOS device. Degradation of the inverter transistors in the stressed ring oscillator in Kim tends to lower the operating frequency of the oscillator. This occurs because the output of a given inverter stage needs to reach a slightly higher voltage to trigger switching of a next inverter stage in cascade, after the transistors in that next inverter have been degraded to operate at a higher threshold voltage. The difference in frequencies between a stressed ring oscillator in which all the cascaded inverters are degraded, versus an identical ring oscillator in which all the inverters are fresh (or at least less degraded), represents a measure of degradation of the stressed ring oscillator. The difference in frequencies of stressed and unstressed ring oscillators is measured in Kim using a phase comparator to produce a beat frequency equal to the frequency difference.
However, one must preliminarily calibrate the two ring oscillators in Kim so both operate at the same frequency before stress is applied to the oscillator to be stressed. It would be desirable if calibration issues could somehow be avoided. Also, generally applying stress to all the cascaded inverters of the stressed ring oscillator does not permit one to distinguish between the effects of NBTI, PBTI, HCI, TDDB, etc. All these effects are lumped together. It would be desirable to have a technique that can test in a way that discriminates among the different degradation types. The stress applied to the inverters of the ring oscillator in Kim is limited to increased bias voltage on the inverters. It would be advantageous if one could test for some of these effects by varying not only the source/drain bias but also varying the gate input voltage, which is not possible except insofar as the high and low output levels of each inverter are affected by the bias voltages to which the inverter is coupled.
According to Keane, J. et al. “An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI and TDDB,” IEEE Journal of Solid-State Circuits, 45:4, pgs. 817-829, April 2010, four ring oscillators can be provided. Two unstressed reference ring oscillators are provided, operated in the same way as the unstressed ring oscillator in Kim, to provide two unstressed-oscillator reference frequencies to be compared against stressed frequencies from the other two oscillators. Keane uses a “back drive” technique wherein the stressed oscillators are operated as ring oscillators only in a measurement mode of operation. In a stressed mode of operation that alternates with the measurement mode, the inverters of one of the oscillators are decoupled from their cascade ring and decoupled from their Vss and Vdd drive voltages, and are separately stressed by coupling with the inverters of another of the oscillators.
Therefore, in the stress mode of operation, the cascaded inverters of the two stressed ring oscillators in Keane are decoupled from a closed loop. One set of cascaded inverters (termed the DRIVE_ROSC) is coupled to bias Vss and Vdd voltages and operated as an open loop string of inverters changing state according to a crock signal at the input. The other set of inverters (BTI_ROSC) is decoupled by switches from both Vss and Vdd bias voltages. Each input and each output of the inverters of BTI_ROSC is coupled to a respective input and output of an inverter of DRIVE_ROSC. This causes the outputs of the cascaded DRIVE_ROSC inverters to reverse bias the gate dielectrics of the BTI_ROSC inverters, and causes BTI stress. The stress switches from producing PBTI in the NMOS elements to producing NBTI in the PMOS elements, respectively, with each input clock. After a time of stress, oscillators are switched again into closed-loop ring oscillator configurations coupled in pairs to phase comparators that determine a beat frequency between the stressed and references oscillators.
At the outset, the oscillators all are adjusted for calibration to the same frequencies. One of the stressed oscillators is stressed by BTI stress alone (in particular by applying a negative gate input voltage to the PMOS transistors in the ring oscillator). The fourth oscillator is subjected to that BTI stress and is also subjected to HCI stress, by switching to a Vdd or Vcc bias of an amplitude greater than nominal. The stressed oscillator frequencies are respectively compared against their reference oscillators to provide difference frequency measures, namely by applying the two reference and two stress oscillator outputs to phase comparators to produce beat frequencies. One difference or beat frequency is related to BTI degradation. The other beat frequency is related to BTI and also HCI degradation. Comparing the two is considered to allow degradation analysis that separates the effects of BTI and HCI. However this test arrangement is not able to test for other degradation effects, notably TDDB. The beat frequency may be low when the difference in frequencies is low.
It would be advantageous to provide a circuit and technique that permits the effects of degradation effects, including HCI, NBTI, PBTI, TDDB to be assessed in isolation from one another. It would also be advantageous to assess these effects while minimizing the need for plural ring oscillators with calibration requirements and switching complication on a large integrated circuit area.